Solid state timer

ABSTRACT

Disclosed is a timer of all solid state components and primarily formed from integrated circuits. The timer comprises a very low frequency oscillator coupled through a divider to an output circuit. In one embodiment, the timer is used to self-destruct a land mine after about twelve hours. In another, it produces an output from a magnetic core ring counter after about a year. Complementary MOSFET&#39;&#39;s are used for the circuit components to minimize power consumption in both embodiments.

United States Patent Martin et al.

Int.

Assignee:

Filed:

Appl. No.:

SOLID STATE TIMER Inventors:

Vincent W. Martin, Lancaster; Bruce G. Steiner, Richland, both of Pa.

us. Cl .Q. ..301/293, 102/702, 307/220,

Cl. ..H03k 17/28 Field of Search ..102/70.2; 307/220, 223, 293,

References Cited UNlTED STATES PATENTS 3/1969 Ball et al ..307/22l7/1970 Katz ....307/288 X 4/1968 Huxster et al.... ..307/293 4/1966 DuVall ..307/234 X DIVIUER 4 DAY 2 DAY RESET [451 Apr. 18, 1972 3,267,3818/1966 Thornberg et al. ..307/220 X 3,469,210 9/1969 Freeman ..331/1l33,513,329 5/1970 Washizuka et al. 307/304 X 3,287,719 11/1966 Thornberget al. 328/48 X 3,006,550 10/1961 Johnson et a1. ...328/39 X 3,350,580lO/ 1967 Harrison ..328/48 X Primary Examiner-Donald D. Forrer AssistantExaminer-R. C. Woodbridge Attorney-Le Blanc and Shur ABSTRACT Disclosedis a timer of all solid state components and primarily formed fromintegrated circuits. The timer comprises a very low frequency oscillatorcoupled through a divider to an output circuit. In one embodiment, thetimer is used to selfdestruct a land mine after about twelve hours. inanother, it produces an output from a magnetic core ring counter afterabout a year. Complementary MOSFETs are used for the circuit componentsto minimize power consumption in both embodiments.

8 Claims, 6 Drawing Figures PULSE INVERTER SHAPER 82 MAGNETIC OUTPUTCORE PULSE RING COUNTER PATEN'I'EDAPR 18 I972 3. 657. 571

SHEET 10? 2 m 30TREM8LER OSCILLATOR DIVIDER SWITCH 28 004 0? cn4oo4 0 522 44 :2 14 I6 NAND RESET 32 TIME CD400? 46 004001 DELAY DETONATOR 5s 2034 :"48

OSCILLATOR INVERTER 44 Z NAND DETONATOR H G. 3 INVENTORS v, w. MARTIN B.STEINER V 12 MRS O BY R1 51; 4 MA ATTORNEYS PATENTEDAPR 18 I972 3,657.571

' SHEET 2 OF 2 OSCILLATOR V DIVIDER 8DAY 2 40 401w PULSE AND RESET'NVERTER SHAPER 80 1a 66 53 I I 32/ MAGNETIC |2HR OUTPUT Y OUTPUT EPULSE He 4 PULS COUNTER MAGNET: CORE RING COUNTER FIG. 6

SOLID STATE TIMER This invention relates to solid state timing devicesand more particularly to an integrated circuit digital timer capable ofinitiating functions over a substantial period of time. Importantfeatures of the invention include the provision of a timing device whichrequires little power, is of small physical size and weight, and whichwill operate reliably in severe environments.

The timer of the present invention is particularly adapted for militaryand related applications where detonator circuits or signal or controlcircuits must be closed after a predetermined time of substantialduration. In one embodiment of the present invention, the timer isparticularly adapted to cause a land mine or similar explosive charge todetonate or selfdestruct after a period of as much as twelve hours. In asecond embodiment, the timer of the present invention is adapted toprovide an electrical output in a lunar surface environment after aperiod of as much as one year.

Timing devices for producing an electrical output after a substantiallength of time are well known. In many instances these take the form ofmechanical devices which are quite bulky and which in many instanceswill not withstand the severe environments to which they may be exposed.Previous electrical devices for producing extended delays have likewiseusually been excessively large and have required large power supplies tosupply the required energy for the electrical components of the system.

The present invention provides an electrical timer which overcomes theseand other disadvantages through the utilization of integrated circuitcomponents which are of relatively small size and weight and which willoperate on a minimum of power for extended periods of time. The basictimer construction takes the form of an integrated circuit low frequencyoscillator which supplies pulses to a utilization device through afrequency divider in the form of a solid state counting chain ofintegrated circuit flip-flops. In one embodiment, the divider output ispassed through a logic circuit to actuate the detonator of an explosivecharge, such as a land mine. In a second embodiment, the output of thedivider is supplied to a ring counter to produce extended periods ofdelay with a minimum of energy drain.

It is therefore one object of the present invention to provide animproved electronic timing device.

Another object of the present invention is to provide an improved solidstate timer for initiating events after a substantial predeterminedperiod of time.

Another object of the present invention is to provide a solid statetimer in which the solid state components require a minimum of energy tooperate.

Another object of the present invention is to provide a solid statetimer made up primarily of integrated circuit components.

Another object of the present invention is to provide a timer comprisingan oscillator and counting chain connected to a magnetic core ringcounter.

Another object of the present invention is to provide a selfdestructdelay circuit for explosive charges, such as are used in land mines.

These and further objects and advantages of the invention will be moreapparent upon reference to the following specification, claims, andappended drawings, wherein:

FIG. 1 is a block diagram of a timer circuit particularly adapted foruse in energizing the explosive charge of a land mine; 7

FIG. 2 is a more detailed diagram of the circuit of FIG. 1;

FIG. 3 shows a waveform of the voltage output for the circuit ofFIGS. land 2;

FIG. 4 is an overall block diagram of a counter constructed inaccordance with the present invention and particularly adapted tooperate on the moon;

FIG. 5 is a circuit diagram of the pulse shaper forming a part of thetimer of FIG. 4; and

FIG. 6 is a detailed circuit diagram of the magnetic core ring counterforming a part of the timer of FIG. 4.

Referring to the drawings, FIG. 1 is a block diagram of a timer,generally indicated at 10 in that FIG., particularly adapted for use ina land mine. The timer comprises an integrated circuit oscillator 12feeding an output signal by way of lead 14 to an integrated circuitdivider 16. Also applied to divider 16 by way of a second lead 18 is areset pulse or signal from reset pulse source 20.

The divider output is connected by way of lead 22 to one input 24 of anintegrated circuit NAND-gate 26. This input of NAND-gate 26 is connectedto the positive side of a power supply (not shown), i.e., power supplyterminal 28, by way of a trembler switch 30. The other input ofNAND-gate 26 is connected to the positive side of the power supplythrough the divider l6 and by way of lead, 32 and arming time delay 34to the other gate input 36.

NAND-gate 26 supplies an output at lead 38 through an inverter 40 to thegate 42 of'a silicon controlled rectifier 44. SCR 44 acts as a switchconnecting a land mine detonator 46 between the positive side 28 andgrounded side 48 of the power supply.

FIG. 2 shows the timer 10 of FIG. 1 with certain components disclosed inmore detail. Oscillator 12 forms a time base which supplies clock pulsesto the divider 16. In the preferred embodiment, oscillator 12 operatesat a rate of one pulse every 5.625 seconds. That is, its pulserepetition rate is l/5.625 per second. The oscillator in the preferredembodiment is of the type shown and described in assignees copendingapplication Ser. No. 802,571, filed Feb. 26, 1969, the disclosure ofwhich is incorporated herein by reference. It is an RC or multivibratortype oscillator utilizing complementary metal oxide silicon field effecttransistors (COM/MOSFET). It is a relatively stable oscillator whichemploys two complementary sections of RCAs COM/MOSFET CD4007, plus aresistor 50 and a capacitor 52.

1 Reset circuit 20 in FIG. 2 comprises a time delay circuit made up ofresistor 54 and capacitor 56 connected to the input of a singlecomplementary section 58 of RCAs COM/MOSFET CD4007. The reset pulse issupplied by lead 18 to the reset tenninal of divider 16. Divider 16 isin the form of a flip-flop counting chain and preferably comprisessufficient stages to divide the output of the oscillator 12 by 2". Thedivider is preferably formed of two RCA COM/MOSFET integrated circuitCD4004. The logic two NAND-gate 26 employs an RCA COM/MOSFET CD4007 andinverter 40 is a single complementary section of RCA CD4007.

The circuit of FIG. 2 is designed to perform the following functions:(a) Become ,operative upon the inception of power to the variouscomponents, (b) introduce a -second delay period for arming the mine(sterile period), (c) after 90 seconds the mine is in the armed positionsuch that when trembler switch 30 within the mine is disturbed, the minedetonates, (d) the mine self-destricts if it has not been disturbedwithin a 12 hour period. These features are all provided in anelectrical circuit construction which has small physical size and weightsince most of the circuit components, including the oscillator, thereset, the divider, the NAND gate, and the inverter, are made ofintegrated circuits and because of the complementary MOSFETconstruction, the timer requires little power and consumes it at a verylow and slow rate.

In operation, when the mine has been installed, the timer is activatedby closure of a suitable manual switch (not shown) connecting thecomponents shown in FIGS. 1 and 2 across the mine power supply, i.e., asmall battery. When the circuit is energized, the reset pulse generator20 acts to provide a high level pulse to set all the stages of thedivider 16 to the same level to insure the proper count of a pulse eachtime the circuit is activated. After the reset generator 20 injects theshort high level pulse, it grounds the reset input of divider 16 toallow proper functioning of the divider.

Divider 16 acts as an accumulator to collect pulses from oscillator 12and, depending upon the number of stages, can give very long timedelays. In one circuit constructed in accordance with the presentinvention, divider 16 was provided with 14 stages and was capable ofproducing one complete cycle in 24 hours as illustrated by the voltagewaveform 60 in FIG. 3 with a 5.625 second pulse input rate. In theactual device constructed, only one-half of the period of the lastdivider stage was used in order to minimize circuitry and parts andimprove reliability. In the circuit, after 12 hours, the positive goingsignal at 62 in FIG. 3 appears at the input to the logic circuit 26 andsince the signal on the other input 36 from the arming time delay(ATD)34 is also a high level signal at the same time, logic circuit 26shifts from a high level to a low level state at its output. It isapparent that the circuitry becomes more involved if the total period of24 hours is used since there is a negative going signal at the end ofthe period.

An arming time delay (ATD) of 90 seconds is introduced by connecting thepower supply through one of the stages of divider 16 to an RC circuit 34whose output is fed to one input 36 of logic circuit 26. By connectingthe power supply signal through the divider, i.e., tapping ofi thedivider, it is possible to use smaller values of resistor and capacitorfor time delay circuit 34 than possible if this circuit were to beconnected directly to the power supply battery. That is, by connectingthrough the divider, it is possible to use physically smaller componentsfor time delay circuit 34 with a corresponding reduction in size andweight.

When the timing circuit is first energized, reset generator 20 suppliesa reset pulse to the divider resetting the stages of the divider to azero state. After 90 seconds, the power supply signal passes through thedivider and the time delay circuit 34 and appears at the input 36 oflogic circuit 26. This 90 second delay period affords the person whosets the mine an opportunity to get away from it before it becomesarmed. Once the mine is armed, actuation, i.e., closing of tremblerswitch 30, causes the power supply voltage to also appear on input lead24 to the NAND or logic circuit 26. Conversely, if the trembler switchis not energized, divider 16 counts the pulses from oscillator 12 and atthe end of 12 hours switches to a high voltage level at output 22 whichis applied to input 24 of the NAND gate. The logic circuit (negative ANDgate) notes all intermediate functions, arm time delay and either thetrembler switch or the divider output, by their level shifts before itproduces an output level change to turn on" the load switching circuit(SCR) 44. Inverter 40 is required at the output of the logic circuit togive a high level signal needed to turn on" the silicon controlledrectifier. Thus, if the trembler switch 30 is activated at any timewhich is more than 90 seconds after the timer is energized but less than12 hours after energization, the mine will detonate since a positive orhigh level signal is applied through switch 30 to one input of the N ANDgate and a second positive or high level signal from the same battery orpower supply is applied by way of the divider and 90 second time timedelay 34 to the other input of the NAND gate. If the trembler switch isnot activated during this period of time, at the end of 12 hours, apositive or high level output signal appears at the output lead 22 ofdivider l6 and this is applied through the NAND gate to cause thedetonator 46 to be activated and the mine to self-destruct at the end of12 hours. An embodiment incorporating a l4-stage divider was constructedin accordance with the present invention and was tested and operatedsatisfactorily with a power consumption rate under 100 microwatts.

FIG. 4 is an overall block diagram of a modified timer constructed inaccordance with the present invention and adapted to provide extremelylong delay times and capable of operation in a moon environment such ason the lunar surface. Specifically, the timer of FIG. 4 is constructedto withstand the extremes of temperature on the lunar surface and toproduce an output pulse one year after energization. In FIG. 4, likeparts bear like reference numerals.

The timer generally indicated at 64 in FIG. 4 again comprises the lowfrequency oscillator 12 and the reset pulse generator 20 in all respectsidentical to the oscillator and reset pulse generator illustrated inFIG. 1. Again, these signal sources apply pulses by way of theirrespective output leads I4 and 18 to the divider 16 which is identicalto the divider previously described in conjunction with FIG. 1 but whichincludes more counting stages. Specifically, divider 16 is provided withsufiicient stages so that its last stage will not change state untilafter 8 days from initiation of timer operation.

In the same manner as previously described, after a period of 12 hours,an output pulse appears on 12 hour output lead 66 and this is applied toa pulse output device 68. Divider 16' is also provided with 8 day outputlead 70, 4 day output lead 72, and 2 day output lead 74. These leads areall connected to the respective inputs of a 3-input logic NAND-gate 26'and its output at lead 38 passes through inverter 40 to a pulse shaper76. From the pulse shaper a signal is fed to a magnetic core ringcounter 78 which, at the end of one year, applies an output pulse tooutput device 80 by way of output lead 82.

FIG. 5 is a more detailed showing of the pulse shaper 76 of FIG. 4. Thepulse shaper comprises a silicon controlled rectifier 84 having a gate86 receiving the output from inverter 40. Connected in series across thepower supply with the SCR 84 is a resistor 88 and capacitor 90 isconnected across the SCR. Also in series with the silicon controlledrectifier are windings 92 and 94 of cores M1 and M2 respectively forminga part of the magnetic core ring counter 78.

FIG. 6 is a detailed showing of the magnetic core ring counter 78 ofFIG. 4. The counter is of conventional construction and comprises aninput lead 96 which receives a signal from the pulse shaper and appliesto the windings 92 and 94 of the magnetic cores M1 and M2. The coreschange state in a well known manner in accordance with the number ofinput pulses until an output is developed on leads 98 and 100 connectedto the last core M and forming the output signal delayed for one yearfrom the initiation of the timer. While a ring counter incorporatingonly 7 stages is illustrated, it is understood that in the preferredembodiment the magnetic core ring counter comprises stages A through Mconstituting thirteen in number.

With the long time counter 64 of FIG. 4 combining a magnetic core ringcounter with a flip-flop counting stage or divider, the magnetic corecounter acts to keep the power consumption to a lower level than thatrequired by the addition of divider stages. In addition, the magneticcore ring counter 78 has the properties of a permanent memorycharacteristic such that when power is removed, the core remembers itslast state.

Timer 64 is specifically designed to perform the following functions:(a) Operate in a lunar environment, such as on the lunar surface, (b) itwill operate for 14 earth days during a lunar day, (c) it is turned offfor 14 earth days during the lunar night (no power is available duringthis period), (d) it supplies an output pulse after one year, (e) it isautomatically self-starting with energization of the battery or otherpower supply, (f) will operate under l-milliampere current consumptionwith a l2-volt supply, and (g) supplies a pulse every 12 hours duringthe lunar day. All of this is provided in a physical package of smallsize and weight, namely, having a 1.25 inch diameter with an overalllength of 2.25 inches.

As previously mentioned, the oscillator and reset circuits are the sameas those previously described. Divider 16' is fonned of three RCAintegrated circuits CD4004. The logic triple gate NAND circuit 26'employs an RCA CD4004. Pulse shaper 76 comprises a silicon controlledrectifier and associated resistor and capacitor as shown in FIG. 5.

The 12 hour pulse is obtained in the same manner as described inconjunction with the embodiment of FIGS. l-3. Triple NAND-gate 26 isused to obtain an output at the end of 14 days, which output pulsedrives the magnetic core ring counter. That is, an output appears atoutput lead 68 when outputs simultaneously appear on leads 70, 72, and74 at the end of 14 days from initiation, i.e., activation of the powersupply or closure of a suitable start switch. When these three signalsare present, a high level signal is fed to the gate of the siliconcontrolled rectifier in the pulse shaper. The load circuit of the pulseshaper is represented by the two cores M1 and M2 of the magnetic corering counter. The ring counter has 13 cores in the memory circuit andthe output is taken ofl of the last core M.

It is apparent from the above that the present invention provides animproved timer and particularly a timer construction which is of smallsize and weight, is very rugged to withstand severe temperature andother environmental conditions, and which gives an accurately timedoutput over relatively long periods of time. This is brought about byincorporating digital counting devices which require a minimum of energyfor operation and which may be formed from integrated circuitcomponents. In one embodiment, the timer is particularly adapted for usein causing an explosive charge, such as a land mine, to self-destructafter a predetermined period of time, and, in a second embodiment, thetimer is adapted to produce an output pulse at the lunar surface after aperiod of as much as one year or more. By combining a divider formed ofseveral stages of complementary MOS circuits with a magnetic core ringcounter, long periods of time may be digitally measured with very lowpower consumption.

The invention may be embodied in other specific forms without departingfrom the spirit or essentical characteristics thereof. The presentembodiments are therefore to be considered in all respects asillustrative and not restrictive, the scope of the invention beingindicated by the appended claims rather than by the foregoingdescription, and all changes which come within the meaning and range ofequivalency of the claims are therefore intended to be embraced therein.

What is claimed and desired to be secured by United States LettersPatent is:

l. A timer comprising an integrated circuit oscillator operating at afrequency below 1 Hz, and an integrated circuit .divider coupled to theoutput of said oscillator, said oscillator 1 via and divider beingfonned of complementary MOSFET's whereby said timer requires a minimumof energy, a logic circuit coupled to the output of said divider, saidlogic circuit comprising a multiple input NAND gate, each input of saidgate being coupled to a difierent stage of said divider, and a magneticcore ring counter coupled to the output of said gate.

2. A timer according to claim 1 including a pulse shaper coupling saidNAND gate to said ring counter.

3. A timer according to claim 2 wherein said pulse shaper includes asilicon controlled rectifier.

4. A timer comprising an oscillator operating at a frequency below 1Hz., a divider coupled to said oscillator to divide the oscillatoroutput, a switch coupled to receive an output from said divider, andincluding a trembler switch coupled to the output of said divider.

5. A timer comprising an integrated circuit oscillator operating at afrequency below 1 Hz., an integrated circuit divider coupled to theoutput of said oscillator, said oscillator and divider being formed ofcomplementary MOSFET's whereby said timer requires a minimum of energy,a logic circuit coupled to the output of said divider, said logiccircuit comprising a 2-input NAND gate, the output of said divider beingcoupled to one gate input, and a time delay circuit coupled to the otherinput of said gate.

6. A timer according to claim 5 including a trembler switch coupled tosaid one gate input.

7. A timer according to claim 6 wherein said time delay circuitcomprises an arming delay circuit for a land mine.

8. A timer according to claim 7 wherein said arming delay circuitcomprises a resistor and a capacitor coupled between said other gateinput and said divider.

UNI'IED STATES PATENT OFFICE CERTH NATE 0E CQRREQHGN Patent No. 3 657 7Dated April 18 1972 lnventofls) Vincent W. Martin and Bruce G. SteinerIt is certified that error appears in the above-identified patent andthat said Letters Patent are hereby corrected as shown below:

In Column 4, line 28, "applies" should read -applies it--; line 61, "RCACD4004" should read -=-RCA CD4007- a Signed and sealed this 19th day ofSeptember 1972o (SEAL) Attest:

EDWARD MeFLETcHEmJRo Attesting Officer ROERT GOTTSCHALK Commissioner ofPatents FORM P0-1050 (10-69) USCOMM-DC 60376-P69 U.S, GOVERNMENTPRINTING OFFlCE1i96B O-JGv-Ud UNITED STATES PATENT OFFICE CERTIFICATE OFCORRECTION April 18, 1972 Patent No. 3 657 571 Dated Inventor s) VincentW. Martin and Bruce G. Steiner It is certified that error appears in theabove-identified patent and that said Letters Patent are herebycorrected as shown below:

In Column 4, line 28, "applies" should read -applies it--; line 61, "RCACD4004" should read --RCA CD4007- Signed and sealed this 19th day ofSeptember 1972.

" (SEAL) Attest:

EDWARD M.FLETCHER,JR. ROBERT GOTTSCHALK Attesting Officer Commissionerof Patents USCOMM-DC 6O376-P69 us. GOVERNMENT HUNTING OFFICE: I96!0-36v-33l FORM PO-IOSO (10-69)

1. A timer comprising an integrated circuit oscillator operating at afrequency below 1 Hz, and an integrated circuit divider coupled to theoutput of said oscillator, said oscillator and divider being formed ofcomplementary MOSFET''s whereby said timer requires a minimum of energy,a logic circuit coupled to the output of said divider, said logiccircuit comprising a multiple input NAND gate, each input of said gatebeing coupled to a different stage of said divider, and a magnetic corering counter coupled to the output of said gate.
 2. A timer according toclaim 1 including a pulse shaper coupling said NAND gate to said ringcounter.
 3. A timer according to claim 2 wherein said pulse shaperincludes a silicon controlled rectifier.
 4. A timer comprising anoscillator operating at a frequency below 1 Hz., a divider coupled tosaid oscillator to divide the oscillator output, a switch coupled toreceive an output from said divider, and including a trembler switchcoupled to the output of said divider.
 5. A timer comprising anintegrated circuit oscillator operating at a frequency below 1 Hz., anintegrated circuit divider coupled to the output of said oscillator,said oscillator and divider being formed of complementary MOSFET''swhereby said timer requires a minimum of energy, a logic circuit coupledto the output of said divider, said logic circuit comprising a 2-inputNAND gate, the output of said divider being coupled to one gate input,and a time delay circuit coupled to the other input of said gate.
 6. Atimer according to claim 5 including a trembler switch coupled to saidone gate input.
 7. A timer according to claim 6 wherein said time delaycircuit comprises an arming delay circuit for a land mine.
 8. A timeraccording to claim 7 wherein said arming delay circuit comprises aresistor and a capacitor coupled between said other gate input and saiddivider.